1. Field of the Invention
The present invention relates to a method for generating a pattern of a photomask used for manufacturing a semiconductor device, a method for manufacturing a semiconductor device, a semiconductor device, and a computer program product for carrying out pattern generation.
2. Description of the Related Art
Along with an increase in speed of semiconductor devices such as large-scale integrated circuits (LSIs), downsizing and higher integration of elements, such as transistors, used in semiconductor devices, are now in progress. In such a semiconductor device, elements and multilevel interconnects are connected to one another by use of conductive via holes, contacts, and the like buried in interlevel dielectric films provided on a wafer. For downsizing and higher integration of semiconductor devices, widths and pitches of interconnects are reduced and an interconnect density in a multilevel interconnect layer is increased. As a result, both interconnect capacitances between interconnects in the same interconnect layer level and between different inter connect layers are increased. Propagation delays in the interconnects due to the increase of the interconnect capacitances inhibit or hinder an increase in speed of a semiconductor device.
In the same interconnect layer, a distribution problem in the interconnect density arises when other interconnects are disposed in the vicinity of the interconnects, which are connected to conductive via plugs and contacts for connection to other interconnect layer. There is a technique to equalize the interconnect density and to reduce the interconnect capacitance by providing a “c-shaped” interconnect portion for increasing the space between an interconnect connected to a conductive via plug or a contact and other interconnect. The spacing is increased more than a distance between the conductive via plug or the contact and the other interconnect (see International Publication WO 01/63673). In addition, a low dielectric constant (low-k) insulating film is used as an interlevel dielectric film to reduce the interconnect capacitance between the different interconnect layers.
For example, in computer-aided design (CAD), pattern processing for generating dummy patterns is executed on a layout of interconnect patterns disposed in a pattern processing area, so that pattern density may exceed a desired reference value. However, the dummy patterns may not be generated when the pattern density in the entire pattern processing area exceeds the reference value. Additionally, when many dense patterns are included in the pattern processing area, even if the pattern density is less than the reference value, it is not possible to increase sufficiently the pattern density in the processing area around an isolated pattern in relation to the reference value by using the dummy patterns generated in the pattern processing area. As a result, although a pattern density in the entire pattern processing area exceeds a desired value, a pattern density around an isolated pattern in the processing area may be less than the reference value. As described above, in the pattern processing area including the isolated pattern and the dense patterns, it is difficult to generate additional patterns, such as dummy patterns, so as to increase the pattern density in the processing area around the isolated pattern.